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AR# 14358

SYNPLIFY 7.1 - How do I pass the new STEPPING attribute through HDL in Synplify?

描述

Keywords: multiplier, step, config, stepping, Virtex, II, Virtex-II

Urgency: Standard

General Description:
How do I pass the new STEPPING attribute that will access the enhanced multiplier speed?

解决方案

Select the "stepping" speed grade for the Virtex-II part, then add the following to your HDL code:

VHDL:

library ieee;
library synplify;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use synplify.attributes.all;

entity mult_test is
port ( <port_list>);

attribute xc_props of mult_test : entity is "CONFIG STEPPING=1";
end entity;
:
:


Verilog:

module mult_test (<port_list>) /*synthesis xc_props="CONFIG STEPPING=1"*/;

:
:

endmodule

For more information about the STEPPING attribute, please see (Xilinx Answer 14339).
AR# 14358
日期 10/15/2002
状态 Archive
Type 综合文章
的页面