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AR# 14360

SYNPLIFY 7.1 - How do I make Synplify infer 3-state (tri-state) buffers in my HDL code?

描述

Keywords: Synplify, 3, tri, three, state, buffer, BUFT, BUFE

Urgency: Standard

General Description:
When I use the following (or something similar):

VHDL:
dout <= din1 when enable = '1' else 'Z';
dout <= din2 when enable = '0' else 'Z';

Verilog:
assign dout = enable ? din1 : 1'bz;
assign dout = enable ? 1'bz : din2;

Synplify 7.x will use LUTs instead of 3-state buffers.

解决方案

Due to simulation mismatches and poorer performance from 3-state buffers, Synplify automatically translates a MUX into gates regardless of whether the use of 3-states has been specified.

A switch that was introduced in Synplify 7.1 allows you to infer 3-state buffers instead of using LUTs:

1. Select "Options".
2. Select "VHDL Compiler" or "Verilog Compiler".
3. Select the "VHDL" or "Verilog" tab.
4. De-select "Push Tristates across Process/Block boundaries".
AR# 14360
日期 04/23/2007
状态 Archive
Type 综合文章
的页面