What is the difference between Bus Functional Model (BFM) and SmartModel (SWIFT interface) simulation? When should I use each?
The PowerPC Core can be simulated with two different models, BFM or SmartModel.
The BFM of the core is a simple functional model that allows you to quickly test the system surrounding the processor. The BFM of the PowerPC Core is essentially a state machine that will generate transactions for the bus interfaces of the Processor: PLB, OPB, or DCR. To all of the peripherals on the bus(es), the processor appears as though there is a full model there; however, only this simple state machine actually exists. This model cannot do any real processing; it can only generate and respond (in a generic manner) to transactions. The transactions generated by this model are defined in a very simple language, the Bus Functional Language (BFL). You create a BFL file that describes the transactions that you would like the processor to produce.
This code initializes some memory of the processor, reads from one address, and writes to another. This simple code will produce the bus transactions on the appropriate bus.
The main reason for performing a BFM simulation is to test a new peripheral. Suppose you create a DSP co-processor for the PowerPC. You might create a BFL file for the PowerPC processor that sends instructions to the DSP processor and reads from it. Creating and changing this BFL file is much faster than simulating the true processor model (SmartModel), running C code that generates the same transactions. The simulation itself also runs much more quickly. Another advantage is that a hardware designer can test the peripheral without requiring its drivers or having any other part of the system build.
BFM simulation is typically performed when new peripherals are created or when behavioral tests are performed on a system.
The SmartModel is the more traditional processor model. It models the exact operation of the processor and includes timing information. It allows you to execute actual compiled code and provides delay information for the logic structures within the processor. Smart model simulation is much slower, but it provides a realistic simulation of latency and simulation of internal logic of the processor that the BFL cannot provide.
SmartModel simulation is typically performed to verify timing in a design or to debug issues in the processor itself.