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AR# 14391

4.2i Virtex-II PAR - Driverless logic 0/1signals are generated in a design using Partial Reconfiguration

描述

Keywords: VCC, PWR, undriven, driver

Urgency: Standard

General Description:
During Partial Reconfiguration Assembly Mode, a VCC signal is left with one load and no drivers. PAR cannot clean up this net; therefore, when BitGen is run, a DRC error is generated.

解决方案

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 2.
AR# 14391
日期 10/23/2008
状态 Archive
Type 综合文章
的页面