General Description: When I run "Check Design Rules" from ISE for a schematic design with a macro that contains FMAP (i.e., "OR8", "OR12", "AND8", etc.), the following error is reported:
"ERROR:HDLParsers:1411 - <file_name.vhf> Line <xx>. Parameter o of mode out can not be associated with a formal port of mode in."
The source of the problem is that the port polarity of output port "o" of the last-stage primitive of the macro (e.g., the last-stage primitive of the macro AND8 is AND2) conflicts with port polarity "o" of the FMAP.
You may also work around this problem by following these steps:
- Push into the macro/symbol in ECS. - Delete the output port from the last-stage primitive (e.g., AND2 for the macro AND8). - Connect a net to the output of AND2 and name it "temp", which will connect to the "o" of the FMAP (this will also change the "o" net of the FMAP to "temp"). - Connect the net "temp" of AND2 to the input of a BUF. - Connect the output of the BUF to an output port (name it "o"). - Save the changes - Return to the ISE GUI and launch "Check Design Rules". - The error is now gone, and the problem is resolved.
Please note that the changes made to the macro are permanent.