General Description When the following cores from CORE Generator are used with IP Update #2 for 4.2i
DDC v1_0 MAC v2_0 SID v2_0 (Interleaver, Deinterleaver)
the following XST errors are reported during synthesis compilation if the design contains more than one COREGen module:
"ERROR:Xst:1068 - inter_blk_rec.v Line 1952. Duplicate declarations of module 'ROC' Module <ROC> compiled."
"ERROR:Xst:1068 - inter_blk_rec.v Line 1964. Duplicate declarations of module 'TOC' Module <TOC> compiled."
Even during synthesis, the simulation wrapper file (<my_core.v>) must be compiled; when the design contains multiple core instantiations, the compiler issues errors regarding the duplicate module declaration of ROC and TOC.
To work around this, comment out all the redundant ROC and TOC module declarations from the wrapper files. The following code (located at the bottom of each wrapper file) should be commented out from all except one wrapper file: