General Description: I have created a new schematic project in the Foundation ALDEC Software tool. I then add a VHDL source file in my project using the "Add Source File(s)" function in the Project Manager window.
The code synthesizes successfully, but when I attempt to create a symbol to add the module in my schematic, the "Create Macro" option in the HDL Editor is greyed out and I cannot use it.
To resolve this problem, copy and paste your VHDL source file into the new project directory that was created by the tool. Then, re-synthesize the VHDL file.