UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14536

Virtex-II Pro Developer's Kit - In the embedded reference design, why do the StrataFlash components appear in a non-3.3V bank?

描述

Keywords: V-II Pro, V2PDK, StrataFlash, Flash, 3.3v, bank, I/O, IO, LOC

Urgency: Standard

General Description:
In the Virtex-II Pro Developer's Kit "embedded reference" design, the StrataFlash components have been mapped to a bank that is not 3.3V-compliant How is this possible?

解决方案

This is an oversight in the example design; StrataFlash components should be placed on a 3.3V-capable bank.

Please adjust the pin LOCs accordingly.
AR# 14536
日期 10/01/2008
状态 Archive
Type 综合文章
的页面