When I perform timing analysis on my DDR OFFSETs with a fixed-phase-shift clock, the analysis does not include the fixed-phased delay for the clock. How do I include the fixed-phase clock delay on my DDR OFFSETs?
Because of a change in the way that the timing tools analyze clock phase shift in software version 4.2isp2, DDR OFFSETs no longer take clock phase shift into account. (NOTE: A patch that will allow all clock phase shift to be taken back into account is available. Please see the information below.)
Fixed Phase Shift and Coarse Phase Shift, which are introduced by DCM phase-shifted clocks (CLK90, CLK180, or CLK270), will be taken into account, as well as rising or falling clock edges. (This is the original behavior of version 4.1i for DDR registers.) Because clock phase will be taken into account, the positive and negative edge flip-flops must be constrained separately.
To install the patch:
1. Copy the $XILINX/virtex2/data/twentry.acd to twentry.acd.bak.
2. Download the "twentry.zip" file from http://www.xilinx.com/txpatches/pub/utilities/fpga/twentry.zip
3. Place the "twentry.acd" into $XILINX/virtex2/data/.
4. Constrain the DDR separately, as explained in (Xilinx Answer 12819).
5. Close Timing Analyzer/TRCE, and re-analyze timing.