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AR# 14714

SYNPLIFY 7.1 - How do I infer ROM using block RAM in Synplify?


Keywords: Synplify, 7.1, ROM, block, RAM, BlockRAM, Virtex, case, constant

Urgency: Standard

General Description:
How do I infer ROM using block RAM in Synplify?


Synplify can infer ROMs using Block SelectRAM rather than LUTs for Virtex, Virtex-E, Virtex-II, and Virtex-II Pro in the following cases:

- For Virtex/Virtex-E, the address line must be between 8 and 12 bits.
- For Virtex-II/Pro, the address line must be between 9 and 14 bits.

The address lines must be registered with a simple flip-flop (no resets, enables, etc.), or the ROM output can be registered with enables or sets/resets; however, you may not use both sets/resets and enables. The flip-flops' sets/resets may be either synchronous or asynchronous.

When asynchronous sets/resets are used, Synplify will create registers with the sets/resets; it will then make these registers either AND or OR with the output of the block RAM.

Please see (Xilinx Answer 8183) for an example of inferring ROM.
AR# 14714
日期 04/23/2007
状态 Archive
Type 综合文章