AR# 1473: Foundation XVHDL: How to control the # of BUFGs which are automatically inserted.
AR# 1473
Foundation XVHDL: How to control the # of BUFGs which are automatically inserted.
描述
Versions: F6.x, F1.3/F1.4
The XVHDL compiler automatically inserts BUFGs on clock signals, according to a limit prescribed by the Foundation Project Manager based on the target device family.
There are cases where the synthesized XNF file will contain more BUFGs than are allowable by the target device architecture.
1. If you instantiate any Global Buffers in the design, these will not be included in the "count".
For example, in an XC5200 design: If you instantiate 2 BUFGs, and have 3 other clock signals in the design, XVHDL will put BUFGs on those 3 clock signals as well, resulting in a design using 5 BUFGs, which is more than the number of BUFGs present in an XC5200 device.
2. If you use the Xilinx_BUFG attribute, these BUFGs will not be included in the "count". Same scenario as above.
So, how can you control the number of BUFGs that XVHDL automatically inserts?
解决方案
There is a command line option for XVHDL which can control this. To allow this option to be used when XVHDL is run from the Foundation GUI, do the following:
Create a file called METAMOR.ARG in your project directory.
In this file, type the following line: -u <n>
where <n> is the number of BUFGs that XVHDL is allowed to automatically insert.
So, for example, in the example above where you have instantiated 2 BUFGs in an XC5200 design, you would want to use the -u 2 option in the Metamor.arg file.