General Description: When I attempt to compile a Verilog source with the stand-alone version of FPGA Express, it fails, even though the source was compiled from the ISE GUI or older version of FPGA Express.
This problem occurs because a default option differs between versions 3.6 and 3.7, or the ISE GUI and the stand-alone version of FPGA Express. The default synthesis engine for FPGA Express 3.7 is the Presto Compiler; the default synthesis engine for FPGA Express versions 3.5 and 3.6 is HDLC. Likewise, in ISE the default setting for the synthesis engine is HDLC (for versions 3.5, 3.6 and 3.7).
To set the synthesis engine in the stand-alone version of FPGA Express, follow these steps:
1. Go to the Synthesis pull-down menu and select "Options". 2. Select the "Project" tab. 3. Select Compatible HDL Compiler - HDLC. 4. Be sure to select "Force Update" before you synthesize.