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AR# 14775

14.x Timing - How do the timing tools find a relationship between two phase-shifted/multiplied clocks?


I have placed a Digital Clock Manager (DCM) in my design that uses multiple outputs. How do the tools find a relationship between the two clocks?


When a PERIOD constraint is applied to an input clock net, NGDBuild pushes that constraint through the IBUFG and the DCM, creating new PERIOD constraints that relate back to the original PERIOD constraint. This is accomplished by using the MULTIPLY/DIVIDE and PHASE attributes on the derived PERIOD constraints.

Q: Must I generate FROM-TO constraints for FFs that are clocked by different outputs of the DCM? Specifically, if an FF on CLK0 feeds an FF on CLK2X (or vice versa), does this need a FROM-TO constraint, or do PAR and TRCE recognize the relationship?

A: The timing tool recognizes the relationship. It sees the frequency factor and the phase relationship, which is all the information needed to calculate the worst-case setup requirement.

Q: Does a non-integer CLKDV divide require an exception constraint between the CLK0 and CLKDV clock domains?

A: A skew-checking code determines the worst-case relationship between the two clock edges and uses it. If this a non-integer, the code simply might have to go past one clock period to find the worst-case time.


DCM outputs CLK0 and CLKDV are used with a CLKDV_DIVIDE setting of 2.5:

Multi-clock example
Multi-clock example

Flip-flops are created that cross both ways across the clock domains. When drawing out the waveform, the worst-case timing from CLK0-to-CLKDV is 5 ns, starting at time 20 ns; this corresponds to the first 5 ns marker in the waveform. Also, the worst-case time for the CLDV- to-CLK0 domain is 5 ns as well, starting at time 25 ns.

Consequently, a 5 ns FROM-TO can be written in either case.

Q: But what does the timing tool do?

Timing Report
Timing Report

A: The timing tool finds the same relationship. It applies 5 ns as the requirement for the cross-clock domain. Notice that TRCE recognizes the times at which these cases occur (20 ns and 25 ns). This is why TRCE lists the clock arrival times.

This process works for almost all relationships between two clocks, including the CLKFX output. However, problems can occur when multiple DCM clocks exist without a common factor between them. In these cases, a FROM-TO constraint is needed.

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf

AR# 14775
日期 12/15/2012
状态 Active
Type 综合文章
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
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