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AR# 14805

4.2i sp3 Timing Analyzer/TRCE/Virtex-II - The DCM PSDONE clock-to-out timing is now relative to PSCLK (rather than CLKIN)

描述

General Description:

Previously, the clock-to-out time of the variable phase shift status signal "PSDONE" was relative to the CLKIN input of the DCM. It is now relative to PSCLK.

解决方案

To include this change in the report, regenerate the timing report using TRCE or Timing Analyzer. Note that PSDONE will take multiple clock cycles to become asserted after PSCLK.

This problem is fixed in the latest 4.2i Service Pack, available at:

http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 3.

AR# 14805
日期 01/18/2010
状态 Archive
Type 综合文章
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