AR# 1481


FGPA Express - How do I use/instantiate pull-ups or pull-downs in FPGA IOBs?


General Description:

How do I use/instantiate pull-ups or pull-downs in FPGA IOBs?


You may specify pull-ups or pull-downs after you have implemented your design. Pull-ups or pull-downs for ports only may be specified in the Constraints GUI.

1. After implementing the design in FPGA Express, right-click on the implemented design in the project window and select "Edit Constraints" to bring up the Constraints window.

2. The Ports display will list all external pins for the design. Within this display, select the "Resistance" column that corresponds to the pin you are seeking. Then, select the type of resistance you would like, either PULLUP or PULLDOWN.

3. Close the Constraints window and optimize the implementation.

(NOTE: Support for pull-ups, pull-downs, and keepers in the Constraints Editor has not yet been added for Virtex devices. To work around this, instantiate these components in your HDL code as described in the next resolution. If the resistor component is to be applied at a port, the I/O component (OBUFT, OFD, etc.) must also be instantiated.)

Pull-ups or pull-downs may also be instantiated in the HDL code. Pull-ups may be instantiated for use with internal logic, and pull-ups or pull-downs may be instantiated for external pins.

VHDL Example (with an IBUF and an AND function):

library IEEE;




entity pullup_test is

Port ( a : in std_logic;

b : in std_logic;

c : out std_logic);

end pullup_test;

architecture Behavioral of pullup_test is

component PULLUP

port (

O : out std_logic);

end component;

component IBUF




end component;

signal hello : STD_LOGIC;

signal middle : STD_LOGIC;


U1: PULLUP port map (O => hello);

U2: IBUF port map (I => hello, O => middle);

U3: c <= (middle and b);

hello <= a;

end Behavioral;

Verilog Example:

PULLUP U1 (.O(signal));


- Pull-downs may only be used with external I/O.

- Pull-ups may be used with external I/O or with internal logic such as 3-state (BUFT, BUFE) or open-drain (DECODE, WAND, WORAND) elements. If pull-ups are instantiated in situations in which they cannot be legally used, FPGA Express will not write them into the XNF file.

- Pull-ups are not required for (or allowed in) XC9500 designs.

It is important to note that you cannot directly drive an input port with a pull-up. Therefore, if you wish to place a pull-up on an input port, you must create a temporary signal that is driven by that input port and use the temporary signal in the pull-up port map.

VHDL Example, placing a pull-up on Input A:

Entity test is

port (A : in std_logic;

B : out std_logic);

end test;

architecture RTL of Test is

component PULLUP

port (O : out STD_LOGIC);

end component;

signal temp : std_logic;


temp <= A;

U1: PULLUP port map (O => temp);
AR# 1481
日期 04/11/2012
状态 Archive
Type 综合文章
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