We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14981

5.1i - PACE pin bank constraints are removed when a UCF is saved in Floorplanner


Keyword: Floorplanner, bank, constraint, PACE

Urgency: Standard

General Description:
I create pin bank constraints in PACE and attempt to create UCF constraints in Floorplanner. After the new constraints are saved in the UCF, the pin bank constraints (e.g., "NET "H0" LOC = "BANK7" ;") are deleted.


To work around this problem:

- Copy the LOC constraints that pertain to BANKs from your UCF and place them into a temporary file after running PACE.
- Open the design in Floorplanner, make the necessary changes to the design, and write out the constraints.
- Then, simply copy the BANK locking constraints from the temporary file and paste them into your UCF.

This issue will be fixed in the next major software release (after 5.1i).
AR# 14981
日期 03/06/2005
状态 Archive
Type 综合文章