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AR# 15026

6.1i HDL Bencher - I can assign values only to individual bits of a bus, not to the entire bus


Keywords: HDL Bencher, ABEL, bus, bits, set

Urgency: Standard

General Description:
When I create a testbench for an ABEL design, a port does not appear as a bus. HDL Bencher will not allow me to assign the entire bus at the same time; instead, I can control only individual bits of the bus.


Be sure to use the correct syntax to declare a bus in ABEL.

For example, instead of declaring a port as:

A7..A0 pin;
new_variable = [A7..A0];

it should be declared as:

BUS [7..0]A pin;
new_variable = A[7..0];
AR# 15026
日期 02/07/2006
状态 Archive
Type 综合文章