VHDL: "# ** Warning: */X_SUH SETUP High VIOLATION ON I WITH RESPECT TO CLK;" "# Expected := 1.8 ns; Observed := 1 ns; At : 341 ns." "# Time: 341 ns Iteration: 3 Instance: /testbench/uut/gsuh_datain_clk."
In many cases, these errors are invalid. The following known issues can cause invalid errors with these external setup and hold checks:
1. Using the DCM to generate a clock The calculations are only valid when the CLK0 output of the DCM is used. The calculations cannot currently account for any phase shifting or period adjustment of the clock. As a result, the checks are invalid when any output other than CLK0 is used. 2. Using differential clocks The checks currently look at the rising edge of both the P and the N side of the clock. This causes the check on the N side to be invalid. 3. Using bidirectional ports These checks are only valid for inputs, but the X_SUH cell is always enabled. As a result, invalid errors may occur when the port is used as an output. 4. Using registers with an enable The X_SUH cell has an enable input, but it is currently tied to VCC. Consequently, errors may occur on a register, even when the enable input of the register is de-asserted.
For information on how the external setup and hold checks are calculated and why they are used, please see (Xilinx Answer 6893).
The checks are disabled until the issues described above are resolved. This disables the external setup and hold checks in the simulation. You should perform thorough static timing analysis on the I/Os instead.
If you are using a software version prior to 5.1.02i, you can disable the insertion of the X_SUH cells by using the following environment variable:
Workstation: setenv XIL_ANNO_DISABLE_GSUH 1
PC: set XIL_ANNO_DISABLE_GSUH=1
Once the environment variable is set, you must run NGDAnno again. In ISE, rerun the Generate Post-Place-and-Route simulation model. This disables the external setup and hold checks in the simulation. You should perform thorough static timing analysis on the I/Os instead.