UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15166

5.1i Timing Simulation - Period and pulse width checks are not adjusted when the CLKIN_DIVIDE_BY_2 property is set on the DCM

描述

Keywords: timing, simulation, DCM, CLKIN_DIVIDE_BY_2

Urgency: Standard

General Description:
When the CLKIN_DIVIDE_BY_2 attribute is used, the period and pulse width checks should be divided by two. However, when I use this attribute, the checks are not being adjusted, and invalid period and pulse width violations occur during simulation.

解决方案

This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 1.
AR# 15166
日期 08/11/2005
状态 Archive
Type 综合文章
的页面