When I use VCS simulation with PhaseAlignEn set to "1", RSClk stops toggling after Reset_n is de-asserted.
This appears to be due to an incompatibility between the Verilog model and the VCS simulator. This issue is currently under investigation. To work around this problem, use static phase alignment (Phase = "0").
For information on additional known issues regarding the PhaseAlignEn signal, please see (Xilinx Answer 15267).