In the VHDL timing simulation netlist, an X_OR gate is inserted into the netlist to OR GSR and the local reset, even though GSR is not used in the design. Why is this done? Are the delays in the SDF on the X_OR gate correct?
This methodology is no longer used in ISE 8.1i and above.
Why is this done?
In the hardware, GSR is asserted during configuration and released when configuration is completed. This occurs regardless of whether the GSR is used in the design. To properly initialize all of the registers in the design, GSR must be pulsed at the beginning of the simulation to simulate the GSR pulse that occurs during configuration. By default, NGD2VHDL will put a 100 ns pulse on GSR at the beginning of the simulation.
To connect both GSR and the Local Reset to each register in the design, these two signals must be ORed together.
Are the delays in the SDF on the X_OR gate correct?
Yes, the delays on the X_OR gate are correct. Typically the delays in the SDF for these OR gates will appear as follows:
This occurs if the local reset is resetting an FF in an IOB. In the above example, the .562ns that was annotated to the OR gate was actually a delay in the IOB. In this case, TRCE specified a Tiorcko value of 1.064ns. (This is the delay to get from the input of the IOB to the FF in the IOB + the recovery time of the FF.) In the SDF, the recovery time of the FF was .502ns. If you add the delay that was annotated to the X_OR gate (.562 ns) and the recovery time of the FF (.502 ns), you get the Tiorcko value (1.064 ns). Again, the delays on the OR gate are true delays and they are correct.