AR# 15333

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5.1i XFLOW - Examples of XFLOW command lines for the "-synth" option are incorrect in the documentation

描述

Keywords: XFLOW, command, example, -synth, -srclist, docs, documentation, syntax

Urgency: Standard

General Description:
XFLOW documentation errors exist regarding command line examples for the "-synth" option.

Corrected examples are given below.

解决方案

(The documentation will be corrected in the next major software release (after 5.1i).)

XST

xflow -p xc2v250fg256-5 -synth xst_vhdl.opt design_name.vhd

If you are using multiple VHDL or Verilog files, you can use a PRJ file that references these files as input.

For example:

xflow -p xc2v250fg256-5 -synth xst_vhdl.opt design_name.prj

Exemplar

xflow -p xc2v250fg256-5 -synth exemplar_vhdl.opt design_name.vhd

If you are using multiple VHDL files, you must list all source files in a text file (one per line) and use the "-g srclist:" file name to switch to XFLOW.

For example:

Assume that the file listing all source files is "filelist.txt" and that "design_name.vhd" is the top-level design:

xflow -p xc2v250fg256-5 -g srclist:filelist.txt -synth exemplar_vhdl.opt design_name.vhd

The same rule also applies to Verilog.

Synplicity

xflow -p xc2v250fg256-5 -synth synplicity_vhdl.opt design_name.vhd

If you are using multiple VHDL files, you must list all source files in a text file (one per line) and use the "-g srclist:" file name to switch to XFLOW.

For example:

Assume that the file listing all source files is "filelist.txt" and that "design_name.vhd" is the top-level design:

xflow -p xc2v250fg256-5 -g srclist:filelist.txt -synth synplicity_vhdl.opt design_name.vhd

(NOTE: There is no space between "srclist:" and "filename".)

The same rule also applies to Verilog.

The following example illustrates the use of a combination of flow types to synthesize and implement a design:

xflow -p xc2v250fg256-5 -synth xst_vhdl.opt -implement balanced.opt testclk.prj

Supported option files for the "-synth" flow type are:

VHDL: xst_vhdl.opt, exemplar_vhdl.opt, synplicity_vhdl.opt.

These option files help optimize a VHDL source file for speed, which reduces the number of logic levels and increases the speed of the design.

Verilog: xst_verilog.opt, exemplar_verilog.opt, synplicity_verilog.opt

These option files help optimize a Verilog source file for speed, which reduces the number of logic levels and increases the speed of the design.
AR# 15333
日期 07/10/2007
状态 Archive
Type 综合文章
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