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AR# 1535

4.1i UNISIMS, SIMPRIMS - What are the Verilog naming rules for user-specified identifiers in Xilinx designs?

Description

Keywords: Verilog, naming, rules, identifier

Urgency: Standard

General Description:
What are the Verilog naming rules for user-specified identifiers in Xilinx designs?

解决方案

1. Although XNF names may contain the characters A-Z, a-z, 0-9, "$", "_", "-", "<", ">" and "/", an identifier in Verilog is any sequence of letters, digits, dollar signs ($), and the underscore symbol (_). Only the following characters are legal in Verilog names:

A-Z, a-z, 0-9, _, and $

2. The first character must not be a digit or "$"; it can be a letter or an underscore symbol.

3. Upper- and lower-case letters are considered to be different (unless the upper-case option is used when compiling).

4. Identifiers can be up to 1024 characters long.

Examples of valid identifiers:

shiftreg_a
busa_index
error_condition
merge_ab
_bus3
n$657
bus_a[0]

4. Escaped identifiers start with the backslash character (\) and provide a means of including any printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal). An escaped identifier ends with white space (blank, tab, new line). Neither the leading backslash character nor the terminating white space is considered to be part of the identifier.

The primary application of escaped identifiers is to translate from other hardware description languages and CAE systems, where special characters may be allowed in identifiers. Escaped identifiers should not be used under normal circumstances.

Examples of escaped identifiers:

\busa+index
\-clock
\***error-condition***
\net1/\net2
\(a,b)
\a*(b+c)
\mybus- [1] (Bit One of bus named "mybus-". This example was found by experimenting with the tools and verifying the result with Cadence.)

(NOTE: Remember to terminate escaped identifiers with white space; otherwise, characters that are supposed to follow the identifier are considered part of the identifier itself.)

5. VHDL and Verilog keywords cannot be used as identifiers.
AR# 1535
创建日期 08/31/2007
Last Updated 08/26/2003
状态 Archive
Type ??????