AR# 15467

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5.1i XST - Logic from function definitions in a package is unexpectedly removed

描述

Keywords: VHDL, ignore, empty

Under certain circumstances, when I synthesize a design with functions defined in a package, all logic associated with that function is removed.

The behavior has been observed with a variable declared in a function that is initialized by the results of another function as shown in the following example:

function add(a,b : std_logic_vector) return std_logic_vector IS
:
:
variable sa : std_logic_vector(max_width-1 downto 0) := extend(a, max_width);
variable sb : std_logic_vector(max_width-1 downto 0) := extend(b, max_width);
:
:

Variables "sa" and "sb" are declared and initialized inside of a function. The initialization occurs as a result of the return value from the function "extend".

解决方案

To work around the problem, initialize the variables after the beginning of the function as shown in this example:

function add(a,b : std_logic_vector) return std_logic_vector IS
:
:
variable sa : std_logic_vector(max_width-1 downto 0);
variable sb : std_logic_vector(max_width-1 downto 0);
:
:
begin
sa := extend(a, max_width);
sb := extend(b, max_width);
:
:
AR# 15467
日期 01/06/2009
状态 Archive
Type 综合文章
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