AR# 15476


5.1i XST - "FATAL_ERROR: Xst:Portability /export/Port_Main.h: 126:1.13/INTERNAL_ERROR:Xst:cmain.c:3181:1.89"


Keywords: XST, register, balancing, Virtex-II, Pro, parameter, Verilog, function

Urgency: Standard

General Description:
XST reports the following error:


This Answer contains a list of known problems related to this error. Even if you find that your problem is described below, please open a case with Xilinx Customer Support at:

Because many of the problems that produce the fatal/internal error are unique, please make sure that you have installed the latest service pack. Service packs are available at:



The following error may be reported when you set the register-balancing option for your Virtex-II Pro design:


This problem is fixed in the latest 5.1i Service Pack, available at:
The first service pack containing the fix is 5.1i Service Pack 1.


XST does not currently support the declaration of parameters inside a function. You can work around this by either using constants in the function or by declaring the parameters in the module in which the function resides.


You can change the following default XST synthesis settings to allow the synthesis of your design:
- Change the FSM option from "Auto" to "None"
- Enable the "Keep Hierarchy" option as follows:
1. Select Edit -> Preferences.
2. Select the Processes tab.
3. Change the Property Display Level from "Standard" to "Advanced".
4. Click the "OK" button.
5. Right-click on the "Synthesis" process.
6. Select "Properties".
7. Under the Synthesis Options tab, select "Keep Hierarchy".


XST reports the fatal/internal error under the following record/array-type conditions:
- The port of a black box is an array of records (which is correctly supported when this is not a black box). To work around this, do not set ports to black boxes as record types.
- The port of an entity is a record, and one of the record fields is multi-dimensional. To work around this, change the record type so that one of the records is not multi-dimensional.
- The port of a module is receiving a vector of an array:
wire [7:0] sig [3:0];

my_mod u0 (.data(sig[0], ...);

To work around this, use a temporary net that connects to the vector and then use that net in the instantiation.
wire [7:0] sig [3:0];
wire [7:0] sig_temp;
assign sig_temp = sig[0];

my_mod u0 (.data(sig_temp, ...);


If you are inferring RAM, XST reports an error if the RAMs are cascaded together (i.e., if the output of one RAM feeds the input of another RAM).

To work around this problem, use CORE Generator to generate your cascaded RAMs.


For some designs, synthesizing the design using an incremental synthesis flow solves this problem. For more information on incremental synthesis as it applies to XST, refer to the XST User Guide in the Xilinx software documentation at:


XST reports this error if a CORE Generator component or a primitive (either in the HDL code or from schematic entry) is instantiated, but is not properly connected. In XST, a proper connection is defined as follows:
- All ports are connected (a connection to a signal/wire that goes nowhere will not work)
- All ports are of the proper type (width, direction)

XST also fails if the underlying core has no logic.

If you cannot connect your CORE Generator core properly, turn "off" the "Read Cores" option in the Synthesize properties under the Synthesis Options tab.


XST errors can also be caused by an order dependency of the process/always blocks. If one process/always block is dependent on the results of another process/always block, move the dependent block so that it is placed after the other block.


Under certain circumstances, an improperly declared alias causes a fatal error in XST.

Many of these issues have been addressed in the latest 5.2i Service Pack, available at:
The first service pack containing the fix is 5.2i Service Pack 1.


Another possible solution is to select the following in Project Navigator:

Project --> Cleanup Project Files

This clears up all of the implementation files created in the background.


This fatal error occurs under certain circumstances when the register balancing switch is "on." To work around this problem, you can turn the register balancing switch "off" (it is "off" by default).
AR# 15476
日期 10/20/2005
状态 Archive
Type 综合文章
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