When I generate a PL4 Core through CORE Generator, the following errors occur:
"ERROR:Failure to create .sym symbol file. Cannot post process .asy symbol file. File C:\test\4_2i\pl4_core.asy does not exist."
"ERROR: Did not generate ISE symbol file for core <pl4_core>."
"WARNING: Warnings and/or errors encountered while generating pl4_core (POS-PHY Level-4 Core 6.0) All outputs products requested may not have been generated."
"ERROR: Elaboration failure for core POS-PHY Level-4 Core."
"WARNING: Not all output products were generated successfully. Please check the console or coregen.log for details."
"ERROR: Elaboration of ore POS-PHY Level-4 Core failed."
These errors occur when you open CORE Generator through ISE Project Navigator, or if the CORE Generator project setting is set to "ISE" or "Foundation." Choosing "ISE" or "Foundation" assumes that the ".sym" symbol file is needed for schematic design.
However, if you are not performing schematic design and the symbol file is not needed, you can continue working with the design, as all necessary VHDL and Verilog files will be generated. SYM, XCO, and XCP files will not be generated.
This issue is fixed in ISE8.2i and SPI-4.2 v8.1 Core by disabling the ASY symbol file generation.
If you need a schematic symbol for an IP core which does not support automatic symbol generation, you can create the symbol as follows:
1. Generate a Verilog or VHDL wrapper for the core during core generation.
2. Add the wrapper to the ISE project.
3. Select the wrapper file in the Sources window.
4. In the Process window, select Design Entry -> Create Schematic Symbol.
5. Remove the wrapper file from the Project Navigator project (do not delete from the project directory).