Keywords: ECS, parser, comma, closepar, unexpected colon, SCH2VHDL, schematic, CORE Generator, COREGen, one bit bus, (0:0), VHDL, XST, LeonardoSpectrum
General Description: If an ECS schematic contains a one-bit input or output written in bus notation (i.e., MYbitBUS(0:0)) and the synthesis flow runs through XST VHDL, the design generates synthesis errors similar to the following:
"Compiling vhdl file E:/data/examples/bidi/hash.vhf in Library work. ERROR:HDLParsers:164 - E:/examples/hash.vhf Line 54. parse error, unexpected COLON, expecting COMMA or CLOSEPAR ERROR:HDLParsers:900 - E:/examples/hash.vhf Line 56. The label xlxi_2 is not declared."
If LeonardoSpectrum VHDL is used for the same design, the following error message is reported:
"e:/examples/hash.vhf", line 54: Syntax Error near ':'."
(NOTE: A CORE Generator component with a 1-bit data-bus output will have a pin with a defined width of (0:0). If you connect this pin directly to another component that has a simple pin connection (no defined width), the same error will occur when you synthesize.)
These errors occur because the SCH2VHDL netlist writer is not handling the one-bit bus correctly.
There are two possible methods of working around the issue:
1. Change the name of the net from "NETNAME(0:0)" to "NETNAME".
2. Use the XST Verilog or LeonardoSpectrum Verilog flow when the design does not contain VHDL macros.