AR# 1554


EDIF 2.0.0 - Naming conventions and translation of escaped Verilog names to EDIF


What are the legal EDIF identifier characters?


According to the EDIF 2.0.0 Reference, a valid EDIF identifier can only contain alphanumeric or underscore characters. In other words, the only legal characters in an EDIF identifier are:

<input> a-z, A-Z, 0-9, _


If the first character of the identifier is not an alphabetic character, it must be prefixed by an ampersand ("&"). In other words, the construct for an EDIF identifier can be described as:

alpha | '&' { alpha | digit | '_' }

NOTE: Forward slashes and backslashes are not legal in an EDIF identifier.

When the Cadence SIR2EDF encounters escaped Verilog names (please refer to (Xilinx Answer 2533)), "\L/R " is mapped by the Cadence SIR2EDF netlister to "&_l_r_". The SIR2EDF netlister also creates a map file, which shows that the identifier "&_l_r_" is mapped to "\l/r ". Such conversions of backslashes and forward slashes may be fairly common in netlists generated by NGD2VER if user-specified names do not conform to Verilog naming restrictions.

AR# 1554
日期 12/15/2012
状态 Archive
Type 综合文章
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