The state assignments for my state machine are listed in the Variable menu, with a default of "Pin." If I change the state assignment variable option to be "Node," the VHDL code generated does not define these in either the port list or the signal list. Because the states are never defined, synthesis fails and an error similar to the following occurs:
"ERROR:HDLParsers:3312 - C:/test/STATE.vhd Line 70. Undefined symbol 'state0'."
The error occurs because two conflicting modes are being used and the generated VHDL code uses part of each mode.
The two modes that cause the conflict are set in the following manner:
1. The user explicitly chooses to expose state variables in one-hot mode by deselecting the "State Assignment," "Hide" box under Options -> Configuration.
2. The user sets the state variables to be internal nodes by changing the individual state variables to "Node" from "Pin" in the variables dialog box (under Options -> Variables).
StateCAD then generates incorrect code. It is hiding the individual state variables because they have been made nodes and it is attempting to expose the nodes because the global setting indicates that they should be exposed.
To work around this problem, check the "Hide" option in the Configuration Menu when the state assignments are listed as nodes. They will then be defined as signals.
Alternatively, you can edit the generated VHD file to add the needed signal declarations.