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AR# 15624

LogiCORE SPI-4.2 (POS-PHY L4)-to-XGMII (10 Gig Ethernet MAC) Bridge v1.0 - In simulation, the bridge does not transfer data correctly from XGMII to PL4


General Description:

NOTE:The following information only applies to ISE 4.2i and VHDL simulation.

When I run a post-NGDBuild or post-route simulation with the PL4-to-10-Gigabit MAC bridge, the bridge does not transfer data correctly from the XGMII interface to the PL4 interface because the PL4 SrcStat output is not updated.


This problem is due to a bug in VHDL BRAM SimPrim models.

A patch to fix the problem is available at the PL4_XGMII Bridge Web page in the Xilinx IP Center at:


The patch is called "cr157340_vhdl_BRAM_patch.zip".

This problem also applies to the PL4 v5.0 core, which requires the same patch file. Please see (Xilinx Answer 15354). If you have already installed this patch for PL4 v5.0, there is no need to install it again.

Patch Installation

NOTE: This patch should only be used with the 4.2i Service Pack 3 software.

To install the patch, follow these steps:

1. Unzip the "cr157340_vhdl_BRAM_patch.zip" file into a temporary directory.

2. Compile unisim_VITAL.vhd (contained in the patch) into the Xilinx UNISIM simulation library. In ModelSim, this is done via the command line as follows:

vcom -87 -work unisim unisim_VITAL.vhd

NOTE: For PL4 designs, RTL simulation is not available at this time, so it is not necessary to perform this step. However, if you are simulating a non-PL4 design in RTL simulation, you must compile unisim_VITAL.vhd.

3. Compile simprim_VITAL.vhd (contained in the patch) into the Xilinx SimPrim simulation library. For ModelSim, this is done via the command line as follows:

vcom -87 -work simprim simprim_VITAL.vhd

Who do I contact for support?

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E-mail: frhelp@xilinx.com


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Hotline: (81) 3-5321-7750

E-mail: jhotline@xilinx.com

This issue is fixed in ISE 5.1i and later software.

AR# 15624
日期 05/03/2010
状态 Archive
Type 综合文章