When I run a design though ISE 5.1i MAP with a PL4 Sink core, the following error is reported:
"ERROR:LIT - PSINCDEC, PSEN, PSCLK and PSDONE of DCM symbol "pl4_snk_top1/pl4_snk_clk0/ StaticAlign_StaticAlign.rdclk_dcm0" (output signal=pl4_snk_top1/pl4_snk_clk0/rdclk0_dcmo) must be driven by active signals if CLKOUT_PHASE_SHIFT is set to VARIABLE."
(NOTE: If the PL4 v5.1 or later versions of this core are used, this problem does not occur.)
This error occurs when the PhaseAlignEn signal is Low. The input to DCM is grounded while it requires the active signal, which may result in the DCM being trimmed altogether.
To work around this issue, instantiate an FDC (flip-flop) onto the PhaseAlignEn signal:
wire Reset = ~Reset_n;
)/* synthesis syn_noprune=1 */;