AR# 15656


LogiCORE SPI-4.2 (POS-PHY L4) v5.0, 5.1i MAP - "ERROR:LIT - PSINCDEC, PSEN, PSCLK and PSDONE of DCM symbol 'pl4_snk_top1/pl4_snk_clk0/StaticAlign_StaticAlign.rdclk_dcm0'"


General Description:

When I run a design though ISE 5.1i MAP with a PL4 Sink core, the following error is reported:

"ERROR:LIT - PSINCDEC, PSEN, PSCLK and PSDONE of DCM symbol "pl4_snk_top1/pl4_snk_clk0/ StaticAlign_StaticAlign.rdclk_dcm0" (output signal=pl4_snk_top1/pl4_snk_clk0/rdclk0_dcmo) must be driven by active signals if CLKOUT_PHASE_SHIFT is set to VARIABLE."


(NOTE: If the PL4 v5.1 or later versions of this core are used, this problem does not occur.)

This error occurs when the PhaseAlignEn signal is Low. The input to DCM is grounded while it requires the active signal, which may result in the DCM being trimmed altogether.

To work around this issue, instantiate an FDC (flip-flop) onto the PhaseAlignEn signal:

wire Reset = ~Reset_n;

FDC PhaseAlignEn_fdc0(

.Q (PhaseAlignEn),

.C (SnkFFClk),

.CLR (Reset),

.D (1'b0)

)/* synthesis syn_noprune=1 */;

AR# 15656
日期 05/03/2010
状态 Archive
Type 综合文章
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