General Description: When the Status pins of the DCM are used, the component declaration must declare the Status as an 8-bit vector in order to match the behavioral model. When only the Status 1 or Status 2 outputs are used, the other ports must be left unconnected. If they are associated with "open" in the port map (STATUS(0)=>open), the following error occurs in ModelSim:
"# ERROR: xxx.vhd(xxx): Formal status must not be associated with OPEN when sub-elements are associated individually."
This problem was fixed in ISE 6.3i.
An alternate way to work around this issue is as follows:
To avoid any errors or warnings, connect the unused Status outputs to unconnected signals. The signal declarations and a snippet of the port map are below:
(NOTE: This change is performed in the ".vhf" file, which is the equivalent VHDL file written out by ECS.)
-- Signal declarations for dummy signals
SIGNAL STATUS7_unconnected : STD_LOGIC; SIGNAL STATUS6_unconnected : STD_LOGIC; SIGNAL STATUS5_unconnected : STD_LOGIC; SIGNAL STATUS4_unconnected : STD_LOGIC; SIGNAL STATUS3_unconnected : STD_LOGIC; SIGNAL STATUS0_unconnected : STD_LOGIC;