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AR# 15712

5.1i XST - An incorrect subtractor is inferred for results larger than 32 bits

描述

Keywords: XST, Verilog, subtract, 32, bit

Urgency: Standard

General Description:
Carry logic "cn" is incorrectly synthesized with the following Verilog design:

module top (a, b, cn, res);
input [31:0] a, b;
output [31:0] res;
output cn;

assign {cn, res} = a - b;
endmodule

解决方案

This problem is fixed in the latest 5.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 2.

The only other way to work around this issue is to keep your subtractors under 32 bits.
AR# 15712
日期 10/20/2005
状态 Archive
Type 综合文章
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