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AR# 15715

5.1i CORE Generator - A Synchronous FIFO schematic symbol contains an SINIT pin that is not connectable


General Description:

After using CORE Generator in ISE 5.1i to generate a Synchronous FIFO, I include the schematic symbol on an ECS sheet.

On the SINIT pin, the small blue square box is located at the wrong end of the port, and the nets do not connect with this SINIT port on the schematic sheet.


You may also select the symbol, use the "Edit Symbol" command to move the blue square to the other end of the line, and save the symbol.

When you return to the schematic editor, a dialog box that describes out-of-date symbols should appear. Update the symbol, then connect a wire to the pin.

If you select "More >>" in the error dialog box, you will see a "Point not on Secondary Grid" error on Line 31 of the .sym file. Edit the point .sym file in a text editor, changing the point "192, 438" to "192, 480".

If you save the .sym, ECS will report that the symbol is out of date; update the symbol.

At this point, you still cannot connect a wire, but you may now edit the symbol and move the blue square to the outside of the pin line (the bottom in the study case). If you close the symbol and update it again, a wire will then connect to the pin.
AR# 15715
日期 07/28/2010
状态 Archive
Type 综合文章