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AR# 15796

3.1 EDK - Does EDK support both VHDL and Verilog?


Keywords: simulation, synthesis, XPS

Urgency: Standard

General Description:
Does EDK support both VHDL and Verilog?


Yes, EDK does support both VHDL and Verilog. This selection is available on the Simulation tab located under Options -> Project Options....

This selection also sets the desired synthesis flow. XPS supports structural and timing simulation in both languages.

Behavioral simulation is supported onlyin the VHDL flow. (Verilog behavioral simulation support will be added in a future release.)
AR# 15796
日期 04/28/2006
状态 Archive
Type 综合文章