AR# 15807


12.1 Known Issue - Timing Analyzer - Timing reports a very large skew on a global clock between flip-flops with BUFGMUX


When I run a design through implementation, why does the timing report show an extremely large skew on my global clock resources between flip-flops?


For more information on PERIOD, see Xilinx White Paper, What are PERIOD Constraints (WP257) at:

This problem commonly occurs when two paths from the same clock pad drive a BUFGMUX. One clock path passes through the DCM, and the other is a non-DCM path. The timing tools use the shortest path for the source flip-flop clock path, which is the DCM clock path. The longest path is used for the destination flip-flop clock path, which is the non-DCM clock path. This creates a large amount of clock skew between these two flip-flops.

To work around this issue, place a TIG constraint on a pin on the BUFGMUX using one of the following examples:

PIN DCM_inst_name.clk0_pin_name TIG


PIN BUFGMUX_inst_name.I1_pin_name TIG

AR# 15807
日期 05/04/2010
状态 Active
Type 已知问题
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