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AR# 15844

5.1i CPLD CoolRunner-II TSim - DataGate does not work in timing simulation when it is applied to a clock net

描述

Keywords: 5.1i, DataGate, Timing Simulation

Urgency: Standard

General Description:
DataGate does not latch clock inputs during timing simulation.

解决方案

This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 2.
AR# 15844
日期 03/05/2006
状态 Archive
Type 综合文章
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