AR# 15845


6.1i MAP/PAR - Is it possible to use a pin-locking constraint to maintain slice pin usage?


Is it possible to lock LUT pins so that PAR does not perform pin-swapping and alter the original pin usage?


Yes. Beginning in the 4.1i software, MAP supports the following constraint and passes it to PAR through the NCD file:

INST "lut_logic" LOCK_PINS ;

where "lut_logic" is any logical instance that will be packed into a Slice LUT (e.g., a LUT3 or AND3).

The placer recognizes the constraint and will not perform any pin-swapping on slices that contain the constraint. This disables pin-swapping for non-LUT pins, as well.

Beginning in the 6.1i software, this constraint will prevent redundant LUT inputs from being trimmed. Prior to this software release, the trimming will occur.

Beginning with version 7.1, the LOCK_PINS constraint has been expanded to support the following use cases for locking individual LUT pins:

Use Case 1: LUT with LOCK_PINS Property

UCF Example: INST "lut_name" LOCK_PINS ;

Result: All LUT pins are locked.

Use Case 2: LUT with LOCK_PINS="ALL" Property

UCF Example: INST "lut_name" LOCK_PINS = "ALL" ;

Result: All LUT pins are locked.

Use Case 3: LUT with LOCK_PINS="I0:A3,I1:A2,I3:A4" Property

UCF Example: INST "lut_name"LOCK_PINS="I0:A3,I1:A2,I3:A4"

Result: The packer will ensure that the physical LUT input assignments are met and will lock those specific pins.

The property value string may be any permutation of a comma-delimited list of logical LUT input names and physical LUT input assignments, as long as the number of LUT inputs indicated by the property value does not exceed the number of input signals assigned to the LUT.

NOTE: Prior to 7.1i, a LOCK_PINS constraint on a LUT symbol would cause all pins of the resulting Slice component to be locked. After 7.1, only the LUT pins explicitly locked as defined above will be locked.

AR# 15845
日期 12/15/2012
状态 Active
Type 综合文章
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