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AR# 1585

UniSim, SimPrim, Simulation - BUFE and BUFT behave differently for front-end and back-end Virtex simulation


Keywords: Verilog, VHDL, SimPrim, UniSim

Urgency: Standard

General Description:
Why is there a discrepancy between UniSim and SimPrim simulation of BUFE and BUFT?


When UniSim simulation models of BUFE or BUFT are used with the 3-state enable "active", the output is a "Z."

However, when SimPrim is used for back-end simulation, the system tools add a pull-up. Therefore, with the 3-state enable "active", the output is a "1." This is the correct behavior.
AR# 1585
日期 10/16/2008
状态 Archive
Type 综合文章