Keyword: Virtex-II, Virtex-II Pro, Pro, configuration, VREF, supply, power
In my Virtex-II (or Virtex-II Pro) design, VREF supplies are connected to the VREF pins on different banks that will be configured as HSTL or SSTL. Prior to configuration, the VREF supply voltage is being pulled higher than I expected.
For example, for a 0.75V VREF for HSTL, prior to configuration, the voltage is actually measured as ~1.2V. When the FPGA is configured, this voltage goes back down to the intended VREF value. Why does this happen?
In the case above, the HSWAP_EN (hot swap enable) pin was tied to the ground pin. This activates the internal pull-ups for user I/O in the device prior to configuration. The VREF pins are the same as user I/O before the device is configured, so the internal pull-ups for these pins will be activated. This configuration acts as a voltage divider, causing the voltage at the pin to rise.
By default, HSWAP_EN is tied High (internal pull-up resistor). For more information, please the Virtex-II/Pro User Guide: Chapter 3, "Configuration" -> Introduction:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide:
Virtex-II Platform FPGA User Guide: