AR# 15966

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Packaging FPGA/CPLD/PROM - Dry Bake Cycle: Is there a maximum number of dry bake cycles that can be performed at 125 C?

描述

General Description:

What does Xilinx recommend for the number of dry bake cycles that can be performed at 125 C?

解决方案

Xilinx recommends that package lots other than Xilinx Flip-Chips are baked not more than two times. Flip-Chips can be baked three times after assembly.

NOTE: Xilinx Flip-Chip packages are still evolving and further testing may change this limit.

AR# 15966
日期 12/15/2012
状态 Active
Type 综合文章
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