We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15993

6.3i Modular Design - The placement of pseudo-TBUFs results in "ERROR:Place:156"


General Description: 

When I run PAR after I place pseudo-TBUFs in my design, the following error occurs: 


"ERROR:Place:156 - The TBUF components listed below, driving the same TBUF signal, have conflicting physical constraints: 


TBUF U1/Q_1[0] (0, 0) Constrained by statement: COMPGRP "AG_U1.TBUF" LOCATE = SITE "TBUF_X0Y47:TBUF_X2Y38" LEVEL 4 ; 


TBUF un6_Q1[0] (3, 0) placed at site TBUF_X6Y41 Constrained by statement: COMP "un6_Q1[0]" LOCATE = SITE "TBUF_X6Y41" LEVEL 1;" 


Because dummy TBUFs should be placed outside the module area groups, the cause of this placement conflict is not clear.


This error occurs when TBUFs are not implemented properly. For information on the proper implementation of TBUFs, please see (Xilinx Answer 12437).

AR# 15993
日期 05/15/2014
状态 Archive
Type 综合文章