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AR# 16104

5.1i ECS - "ERROR:DesignEntry:5 - Bus "iobus(7:4),intbus(3:0)" Some members of this bus are connected to IO Ports, but some are not..."


Keywords: complex, CAT, concatenated, compound, bus, ECS, no load, no source, ISE, WebPACK

Urgency: Standard

General Description:
I have designed a CAT bus that is partially driven from internal logic and partially driven from an I/O. During the schematic check, the following error is reported:

"ERROR:DesignEntry:5 - Bus "iobus(7:4),intbus(3:0)" Some members of this bus are connected to IO Ports, but some are not. All or none of the bus members must be connected to IO Ports."


This error message should not apply to complex or CAT buses. A request has been submitted to fix this.

To work around this error, you will need to buffer the I/O portion of the CAT bus.

In the example above:
- If iobus(7:0) is the I/O pin, connect a buffer to it.
- Name the buffer as an iterative instance (i.e., instname = inbuf(7:0)
- Connect a wire to the opposite side of the iterative buf instance.
- Name the new wire with a unique name (i.e., iobus_buf(7:0)).
- Use the relative portion of the new wire name (i.e., iobus_buf(7:4)) in the CAT bus name in place of the original I/O bus name.
AR# 16104
日期 01/08/2006
状态 Archive
Type 综合文章