We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16232

6.1i COREGen - Async or Sync FIFO ECS schematic symbol has the wrong case, and XST errors report that the ports cannot be found


Keywords: XST, ECS, LogiCORE, Asynchronous, Async, FIFO, schematic, symbol, port, Verilog

Urgency: Standard

General Description:
When I use an Async or Sync FIFO with ECS (in a Verilog synthesis/Simulation flow), the schematic symbol has the wrong case; this causes XST errors to report that the ports cannot be found.


The characters of the ECS schematic symbol created for the FIFO are written in different cases for the ports than those used by the wrapper file for the FIFO. Because the wrapper file is necessary for simulation and synthesis, the fact that Verilog is case-sensitive causes a problem.

To avoid this error, modify the wrapper so that the ports are all written in uppercase characters.
AR# 16232
日期 01/08/2006
状态 Archive
Type 综合文章