We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16435

5.1i Floorplanner - Using Floorplanner to LOC RAM64X1D causes "ERROR:Place... F6 configuration could not be placed..."


Keywords: Floorplanner, LOC, distributed, RAM, 64, dual, port, PAR, error, place, F6

Urgency: Standard

General Description:
When I use Floorplanner to LOC RAM64X1D, the following PAR error is reported:

"ERROR:Place - Structured logic associated with an F6 configuration could not be placed due to a placement constraint. This logic requires a very specific relative placement. The relative placement required by the logic was impossible to resolve.
The following components are involved in this logic:
SLICE ram_1/F5.S1
SLICE SPO_1 locked to site SLICE_X30Y17
This situation can be resolved by fixing the following issue:
This structured logic must be placed in the relative placement form required and with a specific alignment on the CLB-grid. Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked. The location, the logic would be locked to is not correctly aligned. The problem was found at component ram_1/F5.S1 that would have to be locked at site SLICE_X31Y16."


To work around this issue, the coordinate must be the lower left slice in the CLB tile. For Virtex-II devices, both the "x" and "y" coordinates must always be even.

This problem is fixed in the latest 5.2i Service Pack, available at:
The first service pack containing the fix is 5.2i Service Pack 1.
AR# 16435
日期 03/06/2005
状态 Archive
Type 综合文章