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AR# 16506

5.1i HDL Bencher - The "Generate Expected Simulation Results" process is unable to back-annotate file


Keywords: ModelSim, annotate, simulation, expected, .tbw, testbench waveform, HDL Bencher, StateCad, buffer

Urgency: Standard

General Description:
I generated a testbench using HDL Bencher. I then tried to run the process "Generate Expected Simulation Results" which should launch HDL Bencher. Instead the following error message was reported:

"Unable to back-annotate. The most common reasons are:
1. The external simulator needs to be closed to unlock the annotation file.
2. The annotation file does not exist because the annotation test bench has not yet been simulated."

NOTE:The specific error message may vary.


This problem occurs if the source file to be simulated is generated using StateCad.

In the VHDL code generated from a StateCad source file, the keyword "buffer" is causing a problem when running "Generate Expected Simulation Results."

You can work around this problem, by replacing all instances of the word "buffer" with "inout" in your VHDL source code.
AR# 16506
日期 02/07/2006
状态 Archive
Type 综合文章