It is often useful for a device to contain open-drain or open-collector outputs so that multiple outputs can be connected to a single input, such as a reset line.
Can I configure my Xilinx device to include open-drain outputs?
How do I configure my Xilinx device I/O as an open-drain (open-collector)?
With all Xilinx devices, an open-drain type output is not available directly but canbe configured. Schematically, this type of output should look like the following:
This type of circuitry can also be described in HDL code.
Infer the open drain buffer by using the following code:
dout <= 'Z' when din='1' else '0';
DOUT = 1'bZ;
DOUT = 1'b0;