AR# 16510

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Schematic - LOC constraints are not passed to the implementation tools when the constraints are entered in a schematic file

描述

When I insert LOC constraints into my schematic design in ECS, the LOC constraints are not taken into account.

解决方案

In an ISE schematic design, the attribute settings for the LOC constraint can be set to ignore the constraint, which can lead to the above problem. To resolve this, follow the steps below:

1. With the schematic open, right-click the I/O marker.

2. Select "Object Properties".

3. Highlight the LOC attribute. If a LOC attribute does not exist, add a LOC constraint.

4. Select "Edit Traits".

5. Click VHDL or Verilog, depending upon your design flow.

6. If you selected VHDL, ensure that "Write this attribute" is selected. Additionally, select numbers 2 and 3 below "Write this attribute".

7. If you selected Verilog, ensure that "Write this attribute" is selected. Additionally, select number 2 below "Write this attribute".

The LOC constraints can also be entered in the UCF file.

AR# 16510
日期 12/15/2012
状态 Archive
Type 综合文章
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