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AR# 16540

LogiCORE SPI-4.2 (POS-PHY L4) v5.2 - When PAR is run with a PL4 Core, timing errors are reported


General Description:

When I run the ISE 5.1i Place-and-Route (PAR) tool with an SPI-4.2 (PL4) core with SnkClk DCM for a Clk180 selected, the following timing errors appear in the timing report:

"Timing constraint: TS_pl4_snk_top0_pl4_snk_clk0_rdclk180_dcmo = PERIOD

TIMEGRP "pl4_snk_top0_pl4_snk_clk0_rdclk180_dcmo" TS_RDClk_P

/ 1.000000 PHASE + 2.121 nS HIGH 50.000 % ;

163 items analyzed, 18 timing errors detected. (18 setup errors, 0 hold errors)

Minimum period is 4434.064ns.


Slack: -1.551 ns (requirement - (data path - clock skew))

Source: pl4_snk_top0/pl4_snk_io0/StaticAlign_StaticAlign.chan_gen.chan_gen.8.ddr1_gen_ddr1_gen.chan1/ces/Reg3 (FF)

Destination: pl4_snk_top0/pl4_snk_io0/StaticAlign_StaticAlign.chan_gen.chan_gen.8.ddr1_gen_ddr1_gen.chan1/ces/Latch1


Requirement: 0.001 ns

Data Path Delay: 1.552 ns (Levels of Logic = 0)

Clock Skew: 0.000 ns

Source Clock: pl4_snk_top0/RDClk0_GP rising at 0.691 ns

Destination Clock: pl4_snk_top0/RDClk180_GP falling at 0.692 ns"

(Note the above requirement of 0.001 ns.)


This problem was fixed in the 6.1i ISE software release.

This is a known issue associated with how PHASE is calculated in NGDBuild. The tool expects a period that results in a PHASE that is divisible by 2. Otherwise, the above errors occur. (You can view the phase that is generated in the NGDBuild report.)

You can also work around this problem by re-writing the PERIOD constraint in "ps" rather than in "MHz" in the UCF file:

1. Edit the "<component_name>_pl4_wrapper.ucf" file.

2. Replace the constraint:


with the constraint:

TIMESPEC "TS_RDClk_P" = PERIOD "RDClk_P" 2850 ps HIGH 50 %;

3. If the above constraint still reports errors, try other values such as (2849 ps or 2851 ps). The error will not be reported when the calculated PHASE is perfectly divisible by two.

AR# 16540
日期 05/03/2010
状态 Archive
Type 综合文章