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AR# 16546

LogiCORE SPI-4.2 (POS-PHY L4) - List of all Known Issues for PL4 v5.0


General Description:

This Answer Record contains a list of all known issues for the SPI-4.2, also known as POS PHY Level 4 (PL4) v5.0 and v5.1. The list is divided into the following sections:

Constraints and Implementation



Other Helpful Answer Records



Constraints and Implementation:

1. Does the SPI-4.2 (PL4) Core have a required startup sequence or reset procedure?

Please see (Xilinx Answer 16176).

2. In the v5.0 SPI-4.2 (PL4) core, the RSClkPhase static configuration signal sets the relationship between RSClk and RStat. However, this does not currently work under all conditions, and RSClk may be shifted by 90 or even 180 degrees, regardless of the RSClkPhase setting.

Please see (Xilinx Answer 15955).

3. Please do not install 4.2_ip_update3 onto the 5.1i ISE software. The 4.2_ip_update3 contains the SPI-4.2 (PL4) v5.0 core, and this IP update was only tested on the 4.2i software. The use of 4.2_ip_update3 with the ISE5.1i software may cause adverse effects.

Please see (Xilinx Answer 15555).

4. While every attempt was made to keep the constraints as consistent as possible between v4.0 and v5.0, certain modifications are required to update the constraints when a conversion to v5.0 is performed.

Please see (Xilinx Answer 15395).

5. When I run the Xilinx implementation tools, a MAP application reports "ERROR:MapLib:32..."error.

Please see (Xilinx Answer 15454).

6. When I attempt to place BUFGMUX or BUFG in a certain location, the following error is reported in PAR:

"ERROR:Place:1897 - A global clock component <pl4_src_top0/pl4_src_clk0/tsclk_bufg0> configured as a selectable mux is placed in site BUFGMUX3S."

Please see (Xilinx Answer 15673).

7. When BitGen is run with a SPI-4.2 (PL4) core in the design, the following error is reported: "ERROR:DesignRules:524 - Blockcheck: Incomplete DCM configuration".

Please see (Xilinx Answer 14856).

8. When a SPI-4.2 (PL4) core is generated through CORE Generator, the following errors are reported:

"ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\4_2i\pl4_core.asy does not exist."

"ERROR: Did not generate ISE symbol file for core <pl4_core>"

Please see (Xilinx Answer 15493).

9. When I generate a SPI-4.2 (PL4) core v5.0 with the COE file specified, CORE Generator hangs or reports the following errors:

"ERROR: Customization parameter rule checks failed. Terminating core elaboration: Parameter 0 is greater than width 8."

"ERROR: SimGenerator: Failure to set Sim customization parameters for core POS-PHY Level-4 Core."

"ERROR: Elaboration failure for core POS-PHY Level-4 Core."

"ERROR: Elaboration of core POS-PHY Level-4 Core failed."

Please see (Xilinx Answer 15425).

10. Although I selected "LVDS Status Channel I/O" in the POS-PHY Level-4 Core GUI, the UCF file contains pin constraints for LVTTL Status Channel I/O.

Please see (Xilinx Answer 16179).

11. When I use the Xilinx SPI-4.2 (PL4) core and I set the Almost Full Assert/Negate values for the Sink or Source FIFO to be less than 6, data is lost. (An Overflow_n flag is asserted before FFAlmostFull_n is asserted (active Low).)

Please see (Xilinx Answer 16230).

12. When packets are received, the last EOP seems to be stuck in the SnkFFData bus. SnkFFValid is also de-asserted at this time.

Please see (Xilinx Answer 16100).


1. When post-NGDBuild or post-route simulation is run with a SPI-4.2 (PL4) core, the Source status signals on the user interface of the core do not behave properly. Glitches of "X" or "unknown" appear on the SrcStatCh signal, and the SrcStat output is never updated.

Please see (Xilinx Answer 15354).

2. When I simulate a SPI-4.2 (PL4) source core, glitches occur on TDat and TCtl. This is visible on gate-level simulation as well as in timing simulation.

Please see (Xilinx Answer 15579).

3. When an SPI-4.2 (PL4) Sink Core with automatic phase alignment (PhaseAlignEn = 1) is used, VCS simulation does not work. (RSClk may stop toggling after Reset_n is de-asserted.)

Please see (Xilinx Answer 15280).

4. When I simulate an SPI-4.2 (PL4) core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur.

Please see (Xilinx Answer 15578).

5. When an SPI-4.2 (PL4) Sink Core is used with dynamic alignment, the simulation does not behave properly.

Please see (Xilinx Answer 15411).

6. Simulation of the SPI-4.2 (PL4) Core using dynamic alignment requires timing simulation in order to properly simulate the dynamic alignment per-bit de-skew capabilities of the Sink core.

Please see (Xilinx Answer 15436).


1. When Fixed Static Alignment is used, it is necessary to determine the best DCM setting (PHASE SHIFT) to insure that the target system will contain the maximum system margin and perform across voltage, temperature, and process (multiple chips) variations.

Please see (Xilinx Answer 16112).

2. An SPI-4.2 (PL4) Sink core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP-4 error.

Please see (Xilinx Answer 15442).

3. In SPI-4.2 (PL4) Core versions 4.0 and 5.0, the use of automatic static alignment may result in DIP4 errors on the Sink Core. The DIP4 errors appear on the device, but the simulation will not display them.

Please see (Xilinx Answer 15267).

Other Helpful Answer Records:

1. What is the power consumption of the v5.0 SPI-4.2 (PL4) Core?

Please see (Xilinx Answer 16034).

2. A description of error and control signals in addition to the information provided in the SPI-4.2 (PL4) data sheet.

Please see (Xilinx Answer 14968).

3. How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?

Please see (Xilinx Answer 15500).

AR# 16546
日期 05/03/2010
状态 Archive
Type 综合文章